ADVANCED ANALYSIS / TEST

Latch-up

    Latch-up

    • The latch-up test is a modeling test on the creation of a PNPN structure by a parasitic bipolar transistor according to the CMOS circuit configuration, which creates a direct connection path to VDD and GND as the SCR behavior occurs, resulting in the destruction of the element as a continuous overcurrent path.

    Test specification

    Items Consumer / Industrial Automotive
    Latch-up JESD78E AEC-Q100-004